The present invention relates generally to data processing systems, and more particularly, to circuitry for predicting the parity of data within a register in a data processing system.
During the operation of a data processing system, it is often desirable to check data for any processing or transmission errors. One of the most frequently used ways of checking for errors in data is by the use of parity bits. A parity bit is a bit that is transmitted along with an associated data word and indicates the parity of its associated data word, i.e., whether it has an even or an odd number of ones. When a data word reaches its destination along with its parity bit, the parity of the data word is again calculated and compared to the transmitted parity bit. If they are different, an error is known to have occurred somewhere during the transmission of the data word.
Within a data processor, it is also often desirable to check parity each time a data word is passed through a register that may, in response to some control signal, purposely alter the data word. In such a circumstance, a parity check is made by predicting what the parity of the data word will be after it is altered by the register, and then calculating the actual parity on the new data word and making a comparison of the predicted and actual parities.
Circuits for predicting parity are known in the art, with the following being representative patents:
Miller--U.S. Pat. No. 4,079,457 PA1 Cowan--U.S. Pat. No. 3,758,760 PA1 Reinheimer--U.S. Pat. No. 3,699,323 PA1 Keller--et al. U.S. Pat. No. 3,649,817 PA1 Fullton, Jr.--U.S. Pat. No. 3,567,916 PA1 Toy--U.S. Pat. No. 3,555,255 PA1 Cheney--U.S. Pat. No. 3,192,362 PA1 Sakalay--U.S. Pat. No. 3,141,962
In the above mentioned Fullton, Jr. patent, there are disclosed circuits that predict and check parity for a data word in a binary counter and in a shift register. One difficulty with parity prediction circuits, such as those shown in the Fullton, Jr. patent, is that in integrated circuit chips that involve high density gates, such as chips manufactured using emitter-coupled logic (ECL) technology, a register fabricated on the chip can perform a number of different functions with respect to the data stored in the register. For example, in the four stage counter/shift register circuit number F100136, commercially available from Fairchild Camera and Instrument Corporation, Mountain View, California, there are provided control inputs which enable the circuit to perform any one of eight different functions (LOAD, SHIFT DOWN, SHIFT UP, COUNT DOWN, COUNT UP, HOLD, COMPLEMENT and CLEAR). A register circuit of this type and having these functions is now in use or is contemplated for use in many data processing systems. The parity prediction circuits disclosed in the Fullton, Jr. patent, however, are not useable with such a register circuit, since the Fullton, Jr. patent only shows registers having single functions and parity prediction circuits used only in connection with the single functions.
Furthermore, the parity prediction circuits now known frequently involve the use of many gates for receiving the data outputs of their associated registers, such gates being necessary in order to accurately predict the parity which may result from an operation performed by the register. A circuit having more than one function would be made extremely complex and would have a large number of gates if the known circuitry, such as disclosed in the Fullton, Jr. patent, were used to predict parity.